The present invention is related generally to semiconductor integrated circuits, and more specifically to a method and system for electrically coupling a semiconductor chip to a chip package.
During the manufacture of integrated circuit devices, such as memories and microprocessors, a semiconductor die or chip must be physically and electrically attached to a chip package. A chip is a small piece of semiconductor material, such as silicon, in which an integrated circuit is formed, and a chip package as used herein is a protective container, such as a plastic dual-in-line package (DIP), or printed circuit board to which the chip is coupled, as will be appreciated by those skilled in the art.
To electrically couple a chip to a chip package, electrical connections are formed between regions on the chip known as bonding pads, and leads or corresponding bonding pads on the chip package. This process can entail the creation of hundreds of electrical connections between the chip and chip package. Three techniques are generally relied on to accomplish this task: (1) wire bonding; (2) flip chip/bump bonding; and (3) tape automated bonding.
FIG. 1 is a diagram illustrating a chip 2 that is wire-bonded to a chip package 4. Generally, in a wire bonding process a thin wire 6 (commonly between 0.7 to 1.0 mil) is used to connect a chip bonding pad 8 to an inner lead 10 on the chip package 4. Each inner lead 10 is coupled to an outer lead (not shown) which, in turn, provides electrical connections to external circuits (not shown). Each wire 6 must be placed individually, which is time consuming, and each wire results in increased electrical resistance in the connection. In addition, the use of wires mandates the observance of minimum spacing requirements to avoid short circuiting wires and performance problems resulting from wires being too close to one another.
FIG. 2 shows a chip package 4 that is electrically coupled with a chip 2 through flip chip/bump bonding. With flip chip/bump bonding, metal bumps 12 placed on each bonding pad 8 on the chip 2 are soldered to the inner leads 14 of the chip package 4. This is usually done by placing the chip 2 in position on the chip package 4 and melting the metal bumps 12 to solder the bonding pads 8 to the inner leads 14. In this way, all of the bonds necessary to electrically connect a chip 2 to a chip package 4 can be done essentially simultaneously, which reduces the time required to interconnect the chip 2 and chip package 4 when compared to wire bonding. Flip-chip bonding, however, requires precise alignment of the chip 2 and the chip package 4 to ensure proper interconnection. Moreover, great care must also be exerted to prevent soldered metal from causing short circuits by propagating from one bonding pad 8 to adjacent bonding pads. Additionally, given the orientation of the chip 2 and the chip package 4, after bonding an efficient visual inspection of the bonds is not possible, and the nature of the bonding procedure mandates that the chip 2 be heated and exposed to pressure.
Tape automated bonding (TAB) is accomplished through the use of a flexible strip of tape on which a metal lead system has been deposited. Initially a conductive layer is deposited on the tape, usually by methods including sputtering and evaporation. This conductive layer is then formed by mechanical stamping or patterning techniques, such as fabrication patterning, resulting in a continuous tape with multiple individual lead systems. In order to bond the tape to the chip, the chip is then placed on a holder and the tape is positioned over the chip with the inner leads of a lead system on the tape being situated exactly over corresponding bonding pads located on the chip. The inner leads and the bonding pads are then pressed together, creating physical and electrical bonds between the inner leads and the bonding pads. TAB requires very precise positioning of the tape and the chip. Even slight misalignment can result in multiple short circuits and missed connections between inner leads and chip pads, thus compromising the electrical connection of the chip to the chip package.
In view of the above-mentioned processes, it is desirable to develop a new process for electrically interconnecting a chip and chip package.
According to one aspect of the present invention, a chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device.